The present invention generally relates to methods and circuits for power converters, and, in particular, direct-current (DC) to direct-current converters.
In DC/DC converters, after the inductor energy has been discharged into the load and before the inductor energy is replenished via the primary switch, the impedance at some of the nodes becomes high and the parasitic elements cause the node voltages to oscillate. Such oscillation is indicative that the inductor voltage has been totally discharged and the primary switch is off. Referring to FIGS. 1a-1d, an example of a flyback converter and the corresponding voltage levels at the different nodes are illustrated. The flyback converter is generally comprised of a primary control circuit 10 operating a transistor 12 for fluctuating the current passing through coil 14, thereby creating a magnetic field affecting the secondary coils (16, 18). The energy in the secondary subcircuits (20 and 22) generates two outputs. The first output generated by the first subcircuit 20 is fed back to the primary control circuit 10 via an isolated path 24. Each of the subcircuits is comprised of a coil (16, 18) connected in series with a diode (26, 28) and a capacitor (30, 32).
Three other figures are provided to illustrate the voltage or current levels at the various points in the circuit of FIG. 1a. FIG. 1b illustrates the Vgs voltage of the primary switch 12, FIG. 1c illustrates the voltage at node Z, and FIG. 1d illustrates the secondary diode current.
During period A, referring to FIGS. 1b, 1c, and 1d, node Z voltage becomes high when the primary switch is on and the inductor is being charged. During period B, node Z voltage becomes slightly negative, the primary switch is off, and the inductor is being discharged by the load via the diode. Under some operating conditions, the converter goes into an oscillating situation illustrated in period C. When the primary switch is off, the inductor energy has been totally discharged and the diode is off. During period C, impedance at node Z becomes high and its voltage oscillates according to the parasitic elements associated with this node. The same oscillation occurs in other types of DC/DC converters. Such oscillation makes secondary side post regulation (xe2x80x9cSSPRxe2x80x9d) and synchronous rectifier MOSFET (xe2x80x9cSRMOSxe2x80x9d) control difficult.
Referring to FIGS. 2a-2d, a SSRP circuit and corresponding voltage levels are illustrated. The SSRP circuit is similar to the circuit of FIG. 1a. Here, there is a primary control circuit 50 operating a transistor 52 for fluctuating the current passing through coil 54, thereby creating a magnetic field affecting the secondary coils (56, 58). The energy in the secondary subcircuits (60 and 62) generates two outputs. The first output generated by the first subcircuit 60 is fed back to the primary control circuit 50 via an isolated path 64. Subcircuit 60 is comprised of a coil 56 connected in series with a diode 66 and a capacitor 70. Subcircuit 62 is comprised of a coil 58 connected in series with a diode 68, a secondary side transistor (typically a MOSFET) 74, and a capacitor 72. The secondary side transistor 74 is operated by a SSPR PWM circuit 76 with a sensing point at node Z.
As before, three other figures are provided to illustrate the voltage levels at the various points in the circuit of FIG. 2a. FIG. 2b illustrates the Vgs voltage of the primary switch 52, FIG. 2c illustrates the voltage at node Z, and FIG. 2d illustrates secondary side transistor 74 gate voltage (Vgs).
Referring to FIG. 2a, when the SSPR circuit is operated, node Z voltage is used to determine the state of the primary switch. When node Z voltage falls bellow a reference voltage, the SSRP circuit turns on the secondary transistor 74 to regulate the output voltage. However, referring to FIGS. 2b, 2c, and 2d, during period C when node Z voltage is oscillating, the secondary transistor 74 may falsely turn on when node Z voltage drops below a reference voltage 78. As indicated at 80, during period B, the secondary side transistor correctly turns on. As indicated at 82, the secondary side transistor incorrectly turns on when the voltage oscillating and dropping below the reference voltage.
This oscillation also causes problems when a SRMOS converter is used. Referring to FIGS. 3a-3d, a forward DC/DC converter circuit and corresponding voltage levels are illustrated. The SRMOS circuit comprises a primary control circuit 100 operating a transistor 102 for fluctuating the current passing through coil 104, thereby creating a magnetic field affecting the secondary coil 106. The energy in the secondary subcircuit 108 generates an output. Subcircuit 108 is comprised of a coil 106 connected in series with a SRMOS 110, an inductor 112, and a capacitor 114, and connected in parallel with a diode 116. There is a diode 118 across SRMOS 110.
As before, three other figures are provided to illustrate the voltage levels at the various points in the circuit of FIG. 3a. FIG. 3b illustrates the Vgs voltage of the primary switch 102, FIG. 3c illustrates the voltage at node Z and FIG. 3d illustrates the Vgs voltage of the SRMOS 110.
In a forward DC/DC converter such as illustrated in FIG. 3a, when the SRMOS is controlled as a function of the node Z voltage, referring to FIGS. 3b, 3c, and 3d, the SRMOS 110 may falsely turn on (as indicated at 124). This mode of operation typically occurs during light load conditions where the inductor energy is dissipated before the primary switch is turned on. During this period, the impedance at node Z is high and its voltage oscillates according to the parasites associated with this node.
Therefore, there is a desire to have a method/circuit to distinguish between a valid signal or an unwanted oscillating signal resulting from the parasites.
It is therefore an object of the present invention to provide a method and circuit for detection of primary switch status in DC/DC converters.
It is another object of the present invention to provide a method and circuit for distinguishing between a valid signal and a high impedance oscillating signal.
Briefly, a presently preferred embodiment of the present invention provides a method and circuit for detecting primary switch status in isolated DC/DC converters by observing the falling speed of the voltage levels at the sensing point (node Z). It is noted that high impedance oscillation has a relatively slow falling or rising time when compared to a valid signal. By observing the falling or rising time of a given signal during the appropriate time period, a determination can be made to differentiate a valid signal and an oscillating signal. More specifically, two reference voltages are provided to compare against node Z voltage to generate a sense pulse. A reference pulse having a predefined duration is compared to the sense pulse. If the duration of the sense pulse is greater than the duration of the reference pulse, a latch is used to generate a low output signal. If the duration of the sense pulse is less than the duration of the reference pulse, a high output signal is generated. The latch is reset when node Z voltage rises above reference voltage B.
Although the methods and circuits of the present invention is applicable to DC/DC converter circuits, it may be applicable to any and all relevant circuits. Even when standing alone, it can serve as an independent circuit for differentiating different signals by their respective falling and/or rising speeds as indicated by two reference (voltage or current) signals.
An advantage of the present invention is to provide a method and circuit for detection of primary switch status in DC/DC converters.
Another advantage of the present invention is to provide a method and circuit for distinguishing between a valid signal and a high impedance oscillating signal.
These and other features and advantages of the present invention will become well understood upon examining the figures and reading the following detailed description of the invention.